`timescale 1ns/1ps
module sum_n_tb();
   reg         clk;
   reg   [7:0] A;
   reg   [7:0] B;
   wire [15:0] S;
   
   initial begin
      #0 clk = 0;
      forever #10 clk = ~clk;
   end

   sum_n inst_sum_n
     (
      .m_in(A),
      .n_in(B),
      .s_out(S)
      );

   initial begin
      repeat(10)begin
	 B = $random;
	 A = $random;
	 //if(B>=A)begin	 
	    @(posedge clk) begin
	       $monitor("A=%d B=%d S=%d, 0x%0H",A,B,S,S);
	    end
	 //end
      end
      $finish;
   end
   initial begin
      $dumpfile("out.vcd");
      $dumpvars(0, sum_n_tb);
   end
endmodule // sum_n


   
